1. Field of the Invention
The present invention relates to a method according for switching a system clock from a first clock signal to a second clock signal, whereby the switching process is triggered by a select control signal and the switching occurs synchronously to the first and/or second clock signal.
Furthermore, the present invention relates a clock synchronization unit for an electronic system, particularly for a microprocessor having a first input for a first clock signal, a second input for a second clock signal, a third input for a select control signal, and an output for a system clock signal.
In addition, the present invention relates to a processor unit and use of the method of the invention.
2. Description of the Background Art
To control electronic systems, such as a processor unit in the form of a microprocessor, it is normally necessary to make an application-specific selection from a plurality of externally applied asynchronous clock signals. In so doing, depending on the requirement profile, a routine switching among different clock signals to output an accordingly changed system clock signal may be necessary. A switching process of this kind is also necessary, however, especially when one of the external clock signals is incorrect or when an appropriate external clock signal source totally fails.
U.S. Pat. No. 6,873,183 B1 discloses a method and a circuit arrangement for switching a system clock, in which the clock switching from a first clock signal to a second clock signal as a system clock signal occurs asynchronously. According to the disclosure therein, in line with a switch select signal, the clock signal definitive until then as the system clock is immediately “frozen” by an asynchronous state machine, i.e., asynchronously independent of its current state. Then, by means of a known detector, which normally has special, i.e., nonstandard analog circuit elements, the time of transition to the other clock signal, to which the switching is to occur, is determined in the “frozen” state, whereupon the clock signal at this time is switched by the asynchronous state machine from the “frozen” state to the new clock signal, as a result of which undesired spikes in the system clock switching can be avoided.
The previously described circuit arrangement and the method executable with its use have the shortcoming that due to the employed analog circuit elements the synthesis capability by means of common (software) synthesis tools is insufficient, and, moreover, the at least partially analog embodiment of the current asynchronous state machine requires high outlays during manufacture, which makes itself felt in corresponding cost-related disadvantages. In addition, because of the described asynchronous operating mode during switching, clock stretching and shortening occur, which have a negative effect on the behavior of electronic systems controlled by the system clock signal, such as, for example, a microprocessor.
U.S. Pat. No. 5,675,165 and U.S. Pat. No. 6,107,841, however, disclose devices and methods for the synchronous switching of clock signals, which, however, according to the embodiment described therein, can be used in particular only in a relatively limited and inflexible manner. In particular, the subject matter of U.S. Pat. No. 5,675,165, in addition, disadvantageously is excessively complex, because its operating mode is made dependent on a switching direction of the system clock (from high to low frequency or vice versa).